• U. Hübner, U. Gläser and H. T. Vierhaus:
  Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related Defects
  Proc. IEEE Int. Test Conf. 1992
• U. Gläser and H. T. Vierhaus:
  MILEF: An Efficient Approach to Mixed Level Test Generation
  Proc. IEEE EURO-DAC, Hamburg, September 1992
• U. Westerholz and H. T. Vierhaus:
  Library Mapping of CMOS Switch-Level Circuits by Extraction of Isomorphic Subgraphs
  Proc. IEEE ICCD 92, Cambridge, Mass.
• U. Hübner and H. T. Vierhaus:
  Efficient Partitioning and Analysis of Digital CMOS Circuits
  Proc. IEEE ICCAD-92, Santa Clara
• H. T. Vierhaus, W. Meyer, U. Gläser:
  CMOS Bridges and Resistive Transistor Faults: IDDQ versus Delay Effects
  Proc. IEEE International Test Conference, Baltimore, October 1993
• U. Gläser, H. T. Vierhaus, M. Kley, A. Wiederhold:
  Test Generation for Bridging Faults in CMOS ICs Based on Current Monitoring versus Signal Propagation
  Proc. IEEE Int. Conf. on CAD (ICCAD 94), San Jose´, 1994
• R. Wolber, U. Gläser, H. T. Vierhaus:
  Testability Analysis for Test Generation in Synchronous Sequential Circuits
  Proc. ICCD 94, Cambridge, Mass.
• U. Steinhausen, R. Camposano, H. Günther, P. Plöger, M. Theissinger, H. Veit, H. T. Vierhaus, U. Westerholz:
  System Synthesis Using Hardware / Software Codesign
  Proc. Int. Workshop on HW / SW Co-Design, Cambridge, MA, Oct. 1993
• J. Wilberg, R. Camposano, M. Langevin, P. Plöger, H. T. Vierhaus:
  Tools for Generating a VHDL Processor Description and a Compiler Backend from a Single Schematic
  Proc. IFIP Workshop on Logic and Architecture Synthesis, INPG, Grenoble, Dec. 1994
• U. Gläser und H. T. Vierhaus:
  Mixed Level Test Generation for Synchronous Sequential Circuits Using the FOGBUSTER Algorithm
  IEEE Trans. CAD, Vol. 15, No. 4, pp. 410 - 423, 1996
• Uwe Gläser and H. T. Vierhaus:
  FOGBUSTER: An Efficient Algorithm for Sequential Test Generation
  Proc. IEEE EURO-DAC 95, Brighton
• G. van Brakel, U. Gläser, H. G. Kerkhoff, H. T. Vierhaus:
  Gate Delay Test Generation for Non-Scan Circuits
  Proc. EDAC / ETC 95, Paris, pp. 309-313
• F. Corno, U. Gläser, P. Prinetto, M. Sonza Reorda, H. T. Vierhaus:
  Improving Topological ATPG with Symbolic Techniques
  Proc. IEEE VLSI Test Symposium, Princeton (NJ), USA, April 1995
• J. Wilberg, R. Camposano, P. G. Plöger, M. Langevin, H. T. Vierhaus:
  Cosynthesis in CASTLE
  
• in G. Saucier, A. Mignotte:
  Novel Approaches in Logic and Architectural Synthesis
  Chapman & Hall, London, pp. 355 - 366, 1995
• J. Wilberg, A. Kuth, R. Camposano, W. Rosenstiel, H. T. Vierhaus
  Design Space Exploration in CASTLE
  Workshop on High-Level Synthesis Algorithms, Tolls and Design (HILES), Stanford University, Nov. 1995, in: GMD-Studie Nr. 276, Dez. 1995
• J. Wilberg, P. Plöger, R. Camposano, M. Langevin, H. T. Vierhaus
  Codesign of Hardware, Software and Algorithms- A Case Study
  Proc. Int. Symp. Circuits and Systems, Atlanta, GA, 1996
• U. Gläser and H. T. Vierhaus
  FOGBUSTER: An Efficient Algorithm for Sequential Test Generation
  Proc. EURO-DAC 95, Brighton
• G. van Brakel, U. Gläser, H. G. Kerkhoff, H. T. Vierhaus
  Gate Delay Test Generation for Non-Scan Circuits
  Proc. EDAC / ETC 95, Paris, pp. 309-313
• F. Corno, U. Gläser, P. Prinetto, M. Sonza Reorda, H. T. Vierhaus
  Improving Topological ATPG with Symbolic Techniques
  Proc. IEEE VLSI Test Symposium, Princeton (NJ), USA, April 1995
• U. Gläser, H. T. Vierhaus
  Mixed-Level Test Generation for Synchronous Sequential Circuits using the FOGBUSTER Algorithm
  IEEE Transactions of Computer-Aided Design of Ics, Vol. 15, No, 4, April 1996, pp. 410-423
• J. Wilberg, P. Plöger, R. Camposano, W. Rosenstiel, H. T. Vierhaus
  Codesign of Hardware, Software and Algorithms - A Case Study
  Proc. Int. Symp. Circuits and Systems, Atlanta, GA, pp. 552-555, May 1996
• J. Wilberg, A Kuth, R. Camposano, W. Rosenstiel, H. T. Vierhaus
  A Design Exploration Environment
  Proc. of the 6th IEEE Great Lakes Symposium on VLSI, Iowa State Univ., 1996, pp. 77-80
• H. T. Vierhaus, P. Plöger, J. Wilberg
  Hardware-Software Codesign for Embedded Systems: A New Technology or just a New Name?
  Reihe Informatik I-03/1997, Febr. 1997
• H.-Ch. Dahmen, U. Gläser, H. T. Vierhaus
  An Efficient Dynamic Parallel Approach to Automatic Test Pattern Generation
  Prov. IEEE Great Lakes Symposium on VLSI, 1997, pp. 112-117
• H. T. Vierhaus
  Dependable Embedded Systems: Problems and New Solutions for Dependable Hardware
  Reihe Informatik I-11/1997, June 1997
• U. Hübner, H. T. Vierhaus, R. Camposano
  Partitioning and Analysis of Static CMOS Circuits
  IEEE Trans. CAD, Vol. 16. No. 11, pp. 1292-1310, Nov. 1997
• H. Ch. Dahmen, U. Gläser, H. T. Vierhaus
  A Parallel Approach Solving the Test Generation Problem for Synchronous Sequential Circuits
  Proc. PARCO 97, Bonn, August 1997, also Elsevier Publ. Comp., 1998
• M. Pflanz, H. T. Vierhaus
  Generating Reliable Embedded Processors
  IEEE Micro, Sept./Oct. 1998, vol.18, No.5, pp.33-41

Kooperationspartner:

---

GMD-Forschungszentrum - Informationstechnik GmbH, St. Augustin

Thesys GmbH, Erfurt

IHPInstitut für Halbleiterphysik, Frankfurt/Oder

Post-Anschrift:

Brandenburgische Technische Universität Cottbus
Institut für Informatik
Lehrstuhl für Technische Informatik
PSF 101344
03013 Cottbus


Besucheradresse:

BTU Cottbus
Karl-Jannack-Strasse
LG2 - Zi:312


Telefon, Fax:

Tel./Fax.: +49 [0] 355 69 2794

htv@informatik.tu-cottbus.de

[ Zurück zum Anfang]

[ Lehrstuhl-Mitarbeiter]

[ Lehrstuhl-Hauptseite]